T239: Difference between revisions

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NVIDIA T239 SoC ~~Specifications~~

The NVIDIA T239 is a custom SoC designed to Nintendo's specifications. It has many aspects in common with the T234 SoC found in NVIDIA Orin products.

CPU

== Specifications ==

* Eight 64-bit ARM Cortex [https://developer.arm.com/Processors/Cortex-A78C A78C] cores

{| class="wikitable"

|+

Cache

!Component

* 4 MB Shared L3 Cache, 256KB L2 Cache per core, 64KB/64KB (I/D) L1 Cache per core

!Description

|-

Memory ~~Frequency~~

|CPU

* LPDDR5X-3200, 128-bit (102 GB/s)

|Eight 64-bit ARM Cortex [https://developer.arm.com/Processors/Cortex-A78C A78C] cores

|-

Memory Size

|Cache

* 12 GB

|4 MB Shared L3 Cache, 256KB L2 Cache per core, 64KB/64KB (I/D) L1 Cache per core

|-

GPU

|Memory Bus

* Cores 1536-core Ampere GPU

|LPDDR5X-3200, 128-bit (102 GB/s)

|-

|Memory Size

|12GB (2x 6GB)

|-

|GPU

|1536-core Ampere GPU

|}

== Notable Security Features ==

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It is likely that encryption is tweaked on a per-physical-address basis. So, an attacker with control of the external memory bus cannot e.g. relocate data from one address to another.

There is no memory authentication, however. So in the event of external memory tampering, the CPU will read back garbled plaintext (effectively, random bytes).

There is no memory authentication, however. So in the event of external memory tampering, the CPU will read back garbled plaintext (effectively, random bytes). Although, it should in principle be possible to "replay" earlier values from a particular address.

=== XOM (eXecute-Only-Memory) ===

At present it is unknown if/where XOM is used, but the hardware does support it.

@@ Line 1: / Line 1: @@
-NVIDIA T239 SoC Specifications
+The NVIDIA T239 is a custom SoC designed to Nintendo's specifications. It has many aspects in common with the T234 SoC found in NVIDIA Orin products.
-CPU
+== Specifications ==
-* Eight 64-bit ARM Cortex [https://developer.arm.com/Processors/Cortex-A78C A78C] cores
+{| class="wikitable"
+|+
-Cache
+!Component
-* 4 MB Shared L3 Cache, 256KB L2 Cache per core, 64KB/64KB (I/D) L1 Cache per core
+!Description
+|-
-Memory Frequency
+|CPU
-* LPDDR5X-3200, 128-bit (102 GB/s)
+|Eight 64-bit ARM Cortex [https://developer.arm.com/Processors/Cortex-A78C A78C] cores
+|-
-Memory Size
+|Cache
-* 12 GB
+|4 MB Shared L3 Cache, 256KB L2 Cache per core, 64KB/64KB (I/D) L1 Cache per core
+|-
-GPU
+|Memory Bus
-* Cores 1536-core Ampere GPU
+|LPDDR5X-3200, 128-bit (102 GB/s)
+|-
+|Memory Size
+|12GB (2x 6GB)
+|-
+|GPU
+|1536-core Ampere GPU
+|}
 == Notable Security Features ==
@@ Line 28: / Line 35: @@
 It is likely that encryption is tweaked on a per-physical-address basis. So, an attacker with control of the external memory bus cannot e.g. relocate data from one address to another.
-There is no memory authentication, however. So in the event of external memory tampering, the CPU will read back garbled plaintext (effectively, random bytes).
+There is no memory authentication, however. So in the event of external memory tampering, the CPU will read back garbled plaintext (effectively, random bytes). Although, it should in principle be possible to "replay" earlier values from a particular address.
 === XOM (eXecute-Only-Memory) ===
 At present it is unknown if/where XOM is used, but the hardware does support it.