Hardware: Difference between revisions

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 === DRAM Layout ===
-The footprint is BGA-441, as defined by JEDEC [https://www.jedec.org/standards-documents/docs/jesd209-5c JESD209-5C] (LPDDR5X). This annotated image shows the signals routed on the top layer of the PCB, for the IC south of the SoC. The signals routed here are CS0-1, CA0-6, and CK, for each of the four channels.
+The footprint is BGA-441 (JEDEC [https://www.jedec.org/standards-documents/docs/mo-342a MO-342]), with ballout defined by JEDEC [https://www.jedec.org/standards-documents/docs/jesd209-5c JESD209-5C] (LPDDR5X). This annotated image shows the signals routed on the top layer of the PCB, for the IC south of the SoC. The signals routed here are CS0-1, CA0-6, and CK, for each of the four channels.
 [[File:Dram traces annotated.jpg|frameless|619x619px]]