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Add DRAM trace annotation image |
Link to JEDEC MO-342 package spec |
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=== DRAM Layout === | === DRAM Layout === | ||
The footprint is BGA-441, | The footprint is BGA-441 (JEDEC [https://www.jedec.org/standards-documents/docs/mo-342a MO-342]), with ballout defined by JEDEC [https://www.jedec.org/standards-documents/docs/jesd209-5c JESD209-5C] (LPDDR5X). This annotated image shows the signals routed on the top layer of the PCB, for the IC south of the SoC. The signals routed here are CS0-1, CA0-6, and CK, for each of the four channels. | ||
[[File:Dram traces annotated.jpg|frameless|619x619px]] | [[File:Dram traces annotated.jpg|frameless|619x619px]] | ||
Revision as of 01:32, 26 June 2025
Motherboard
Nintendo Switch 2
| Product Code | Description |
|---|---|
| BEE-CPU-01 | Retail Nintendo Switch 2 |
DRAM Layout
The footprint is BGA-441 (JEDEC MO-342), with ballout defined by JEDEC JESD209-5C (LPDDR5X). This annotated image shows the signals routed on the top layer of the PCB, for the IC south of the SoC. The signals routed here are CS0-1, CA0-6, and CK, for each of the four channels.
Specifications
Nintendo Switch 2
| Component | Description |
|---|---|
| SoC | NVIDIA GMLX30-A1 |
| Screen | Innolux ZD079KA-03A |
| Storage | Toshiba/Kioxia THGJFGT1E45BAILHW0 256 GB UFS 3.1 or SKhynix HN8T15DEHKX075 256 GB UFS 3.1 |
| Memory | SKhynix H58GE6AK8BX107 6 GB LPDDR5X DRAM x2 (12GB total)
or Samsung K3KL2L20DM-JGCT 6 GB LPDDR5X DRAM x2 (12GB total) |
| Wifi/BT | MediaTek MT3681AEN |
| PMIC | Maxim Integrated MAX77851SAWJ+T |
| Sub-PMIC | Renesas/Dialog DA9092-AIOV2 |
| Audio | Realtek ALC5658 |
| Voice | Intelligo Technology IG2200 |
| USB 2.0 Hub | Genesys Logic GL852G-OHY60 |
| USB-C | Cypress CYPD6228-96BZXI (CP10359AT) |
| GC ASIC | B2349 GCBRG HAC STD T2010423 |